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programmable high- g digital impact sensor and recorder adis16204 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features dual-axis sensing, 70 g , 37 g 14-bit resolution impact peak-level sample and hold rss output programmable event recorder 400 hz double-pole bessel sensor response digitally controlled sensitivity and bias digitally controlled sample rate, up to 4096 sps programmable condition monitoring alarms auxiliary digital i/o digitally activated self-test embedded temperature sensor programmable power management spi-compatible serial interface auxiliary 12-bit adc input and dac output single-supply operation: +3.0 v to +3.6 v 4000 g powered shock survivability applications crash or impact detection condition monitoring of valuable goods safety, shut-off sensing impact event recording security sensing, tamper detection functional block diagram sclk din dout cs rst dio1 dio2 spi port temperature sensor self-test power management auxiliary i/o event capture buffer memory alarms digital control signal conditioning and conversion digital processing adis16204 vdd com a ux adc aux dac vref inertial mems sensor 06448-001 figure 1. general description the adis16204 is a fully-contained programmable impact sensor in a single compact package enabled by the analog devices, inc. i sensor? integration. by enhancing the analog devices i mems? sensor technology with an embedded signal processing solution, the adis16204 provides tunable digital sensor data in a convenient format that can be accessed using a serial peripheral interface (spi). the spi provides access to measurements for dual-axis linear acceleration, a root sum square (rss) of both axes, temperature, power supply, an auxiliary analog input, and an event capture buffer memory. easy access to digital sensor data provides users with a system-ready device, reducing development time, cost, and program risk. unique characteristics of the end system are accommodated easily through several built-in features, such as a single command in-system bias null/offset calibration, along with convenient sample rate control. the adis16204 offers the following embedded features, which eliminate the need for external circuitry and provide a simplified system interface: ? peak sample and hold ? programmable event recording (dual, 1k 16 bit) ? rss output (total shock in the x-y plane) ? configurable alarms ? auxiliary 12-bit adc and dac ? configurable digital i/o port ? digital self-test function the adis16204 offers two power management features for managing system-level power dissipation: low power mode and a configurable shutdown feature. the adis16204 is available in a 9.2 mm 9.2 mm 3.9 mm laminate-based land grid array (lga) package with a tem- perature range of ?40c to +105c.
adis16204 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 recommended pad geometry .................................................... 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 10 overview ...................................................................................... 10 acceleration sensor .................................................................... 10 temperature sensor ................................................................... 10 impact/shock response ............................................................ 10 auxiliary adc function ........................................................... 11 basic operation .............................................................................. 12 serial peripheral interface ......................................................... 12 data output register access .................................................... 13 programming and control ............................................................ 14 control register overview ....................................................... 14 control register structure ........................................................ 14 global commands ..................................................................... 15 calibration ................................................................................... 15 operational control ................................................................... 16 status and diagnostics ............................................................... 17 alarm detection and event capture ....................................... 18 second-level assembly ................................................................. 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 6/07revision 0: initial version
adis16204 rev. 0 | page 3 of 24 specifications t a = ?40 o c to +105c, vdd = 3.3 v, unless otherwise noted. table 1. parameter conditions axis min typ max unit accelerometer output full-scale range x 70 g y 37 g sensitivity x 17.125 m g /lsb y 8.407 mg /lsb nonlinearity 0.2 % sensor-to-sensor alignment error 0.1 degrees cross-axis sensitivity ?5 +5 % resonant frequency 24 khz offset zero- g output 1 x 0.2 g y 0.2 g noise noise density 10 hz ? 400 hz, no postfiltering 1.8 m g / hz frequency response sensor bandwidth (?3 db) 2-pole bessel 360 400 440 hz temperature drift |25c ? t min | or |t max ? 25c| 2 hz accelerometer self-test state 2 output change when active at 25c x 254 lsb output change when active y 518 lsb temperature sensor output at 25c 1278 lsb scale factor ?2.13 lsb/c adc input resolution 12 bits integral nonlinearity (inl) 2 lsb differential nonlinearity (dnl) 1 lsb offset error 4 lsb gain error 2 lsb input range 0 2.5 v input capacitance during acquisition 20 pf on-chip voltage reference 2.5 v accuracy at 25c ?10 +10 mv reference temperature coefficient 40 ppm/ o c output impedance 70 dac output 5 k/100 pf to gnd resolution 12 bits relative accuracy for code 101 to code 4095 4 lsb differential nonlinearity (dnl) 1 lsb offset error 5 mv gain error 0.5 % output range 0 to 2.5 v output impedance 2 output settling time 10 s
adis16204 rev. 0 | page 4 of 24 parameter conditions axis min typ max unit logic inputs 3 input high voltage, v inh 2.0 v input low voltage, v inl 0.8 v logic 1 input current, i inh v ih = vdd 0.2 1 a logic 0 input current, i inl v il = 0 v ?40 ?60 a input capacitance, c in 10 pf digital outputs output high voltage, v oh i source = 1.6 ma 2.4 v output low voltage, v ol i sink = 1.6 ma 0.4 v sleep timer timeout period 4 0.5 128 seconds start-up time initial 130 ms reset recovery 2.5 ms flash memory endurance 5 20,000 cycles data retention 6 t j = 85c 20 years conversion rate maximum throughput rate 4096 sps minimum throughput rate 2.066 sps power supply operating voltage range, vdd 3.0 3.3 3.6 v power supply current normal mode, smpl_time 0x08 (f s 910 hz), at 25c 12 15 ma fast mode, smpl_time 0x07 (f s 1024 hz), at 25c 37 43 ma sleep mode, at 25c 150 a 1 note that gravity can impact this number, zero- g condition assumes both axes oriented normal to the earths gravity. 2 self-test response changes as the square of vdd. 3 note that the inputs are +5 v tolerant. 4 guaranteed by design. 5 endurance is qualified as per jedec st andard 22, method a117 and measured at ?40c, +25c, +85c, and +105c. 6 retention lifetime equivalent at junction temperature (t j ), 55c as per jedec standard 22, method a117. retention li fetime decreases with junction temperature.
adis16204 rev. 0 | page 5 of 24 timing specifications t a = +25c, v cc = +3.3 v, unless otherwise noted. table 2. parameter description min 1 typ max 1 unit f sclk fast mode 2 0.01 2.5 mhz normal mode 2 0.01 1.0 mhz t datarate chip select period, fast mode 2 40 s chip select period, normal mode 2 100 s t cshigh chip select high 1/f sclk t cs chip select to clock edge 48.8 ns t dav data output valid after sclk edge 100 ns t dsu data input setup time before sclk rising edge 24.4 ns t dhd data input hold time after sclk rising edge 48.8 ns t df data output fall time 5 12.5 ns t dr data output rise time 5 12.5 ns t sfs cs high after sclk edge 5 ns 1 guaranteed by design; typical specifications are not tested or guaranteed. 2 based on sample rate selection. cs s cl k t datarate 06448-002 figure 2. spi chip select timing cs sclk dout din 123456 1516 w/r a5 a4 a3 a2 d2 msb db14 d1 lsb db13 db12 db10 db11 db2 lsb db1 t cs t sfs t dav t dhd t dsu 06448-003 figure 3. spi timing (utilizing spi settings typically identified as phase = 1, polarity = 1)
adis16204 rev. 0 | page 6 of 24 absolute maximum ratings table 3. parameter rating acceleration (any axis, unpowered, 0.5 ms) 4000 g acceleration (any axis, powered, 0.5 ms) 4000 g v cc to com ?0.3 v to +6.0 v digital input/output voltage to com ?0.3 v to +5.5 v analog inputs to com ?0.3 v to +3.5 v operating temperature range ?40c to +125c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adis16204 rev. 0 | page 7 of 24 pin configuration and fu nction descriptions a u x a d c v d d v r e f c o m n c n c d i o 2 d i o 1 nc = no connect sclk dout din cs aux dac nc nc rst adis16204 top view (not to scale) 1 x y 4 3 2 12 9 10 11 56 7 8 13 16 15 14 06448-004 notes 1. pins are not visible from the top view. they are shown for convenience in creating cad library parts. figure 4. pin configuration table 4. pin function descriptions pin no. mnemonic type 1 description 1 sclk i spi, serial clock. 2 dout o spi, data out. 3 din i spi, data in. 4 cs i spi, chip select, active low. 5, 6 dio1, dio2 i/o multifunction digital input/output pins. 7, 8, 10, 11 nc C no connect. 9 rst i reset, active low. this input resets th e embedded microcontroller to a known state. 12 aux dac o auxiliary dac analog voltage output. 13 vdd s +3.3 v power supply. 14 aux adc i auxiliary adc analog input voltage. 15 vref o precision reference output. 16 com s common. reference point for all circuitry. 1 s = supply; o = output; i = input. recommended pad geometry 06448-005 0.670 12 1.127 16 4.1865 8 2.6955 8 5.391 4 8.373 2 0.500 16 9.2mm 9.2mm stacked lga package figure 5. example of a pad layout
adis16204 rev. 0 | page 8 of 24 typical performance characteristics 0.040 0.125 0.210 0.295 0% 10% 20% 30% 60 % 50% 40% 06448-025 % of population offset bias ( g ) figure 6. bias offset distribution, x-axis 0.045 0.040 0.125 0.295 0.210 0% 5% 10% 15% 20% 25% 30% 35% 40% 45% 50% 06448-026 % of population offset bias ( g ) figure 7. bias offset distribution, y-axis 0.4 0.6 0.8 0.2 0 ?0.2 ?0.4 ?40 0 40 80 120 x-axis bias offset ( g ) temperature (c) ?1 sigma +1 sigma 06448-015 figure 8. offset bias change vs. temperature, x-axis 0.4 0.5 0.2 0.3 0.1 0 ?0.2 ?0.1 ?0.3 ?0.4 ?40 0 40 80 120 y-axis bias offset ( g ) temperature (c) ?1 sigma +1 sigma 06448-016 figure 9. offset bias change vs. temperature, y-axis 35 20 25 30 15 10 5 0 % of population total offset bias change ( g ) 0 0.020.040.060.080.100.120.140.16 0.18 06448-019 figure 10. offset bias change, x-axis vs. power supply (3.0 v to 3.6 v) 25 20 15 10 5 0 % of population total offset bias change ( g ) 0 0.010.020.030.040.050.060.07 0.08 06448-020 figure 11. offset bias change, y-axis vs. power supply (3.0 v to 3.6 v)
adis16204 rev. 0 | page 9 of 24 0 5 10 15 20 25 30 0.0170 0.0172 0.0174 0.0176 0.0178 0.0180 % of population sensitivity ( g /lsb) 06448-027 figure 12. x-axis sensitivity distribution supply current (ma) supply voltage (v) 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 high performance mode normal mode 0 5 10 15 20 25 30 35 40 06448-023 figure 13. supply current vs. supply voltage sleep current (a) temperature (c) ?50 ?35 ?20 ?5 10 25 40 55 70 85 100 0 400 300 200 100 06448-032 +1 sigma ?1 sigma figure 14. sleep current vs. temperature 4.3 4.5 4.1 3.9 3.7 3.5 self-test response ( g ) temperature (c) ?60 ?40 ?20 0 20 40 60 80 100 120 0 6448-022 figure 15. self-test response (x and y axes) vs. temperature 0 20406080100120 ?50 0 50 100 150 200 acceleration magnitude ( g ) sample x_accl y_accl actual acceleration profile 0 6448-029 figure 16. overrange recovery, sample rate = 4096 sps
adis16204 rev. 0 | page 10 of 24 theory of operation overview the adis16204 integrates a dual-axis 70 g/37 g mems acceleration sensor into a complete impact/shock measurement and recording system. the integrated mixed signal processing circuit digitizes the sensor data, applies corrections factors, provides many user-programmable features, and offers a simple communication conduit: the serial peripheral interface (spi). acceleration sensor the adis16204 base sensor core provides a fully differential sensor structure and circuit path, resulting in substantial rejection of electromagnetic interference (emi) effects. it uses electrical feedback with zero-force feedback for improved accuracy and stability. the sensors resonant frequency is well beyond the cut-off frequency of the filter, which adds further noise rejection to the sensor signal conditioning circuit. unit sensing cell movable frame fixed plates unit forcing cell anchor moving plate plate capacitors acceler a tion anchor 0 6448-006 figure 17. simplified view of sensor under acceleration figure 17 is a simplified view of one of the differential sensor elements. each sensor includes several differential capacitor unit cells. each cell is composed of fixed plates attached to the substrate and movable plates attached to the frame. displace- ment of the frame changes the differential capacitance, which is measured by the on-chip circuitry. complementary 200 khz square waves drive the fixed plates. electrical feedback adjusts the amplitudes of the square waves such that the ac signal on the moving plates is 0 v. the feedback signal is linearly proportional to the applied acceleration. this unique feedback technique ensures that there is no net electro- static force applied to the sensor. the differential feedback control signal is also applied to the input of the filter, where it is filtered and converted to a single-ended signal. temperature sensor this sensor reflects the sensors junction temperature and provides a convenient temperature measurement for system- level characterization and calibration feedback. impact/shock response the sensors mechanical structure provides a linear meas- urement range that is 8 times that of each axis actual output measurement range. therefore, when considering the response to high- g , short duration events, the 2-pole, 400 hz, low-pass bessel filter network influences the output response. figure 18 provides a frequency response for this signal chain. in figure 19 , the x-axis accelerometer experiences a 560 g shock event that lasts 0.1 ms, causing the output response to reach 70 g . for users that need to avoid output saturation, keeping the integration of the events acceleration response (acceleration-time product in the case of figure 19 ) below 56 g -ms is critical. 10 0 ?20 ?10 ?30 ?40 ?50 10 100 1k 10k magnitude (db) frequency (hz) x: 418.9 y: ?3.291 06448-007 figure 18. adis16204 frequency response 0 50 100 150 200 250 300 350 400 450 500 550 600 ?0.50 ?0.25 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 impact magnitude ( g ) time (ms) 560 g , 0.1ms, simulated shock 70 g , filtered response 06448-008 figure 19. adis16204 shock response
adis16204 rev. 0 | page 11 of 24 auxiliary adc function the auxiliary adc function integrates a standard 12-bit adc into the adis16204 to digitize other system-level analog sig- nals. the output of the adc can be monitored through the aux_adc control register, as defined in table 6 . the adc is a 12-bit successive approximation converter. the output data is presented in straight binary format with the full-scale range extending from 0 v to v ref . a high precision, low drift, factory calibrated 2.5 v reference is also provided. figure 20 shows the equivalent circuit of the analog input struc- ture of the adc. the input capacitor (c1) is typically 4 pf and can be attributed to parasitic package capacitance. the two diodes provide esd protection for the analog input. care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mv. this causes the diodes to become forward-biased and to start conducting. the diodes can handle 10 ma without causing irreversible damage. the resistor is a lumped component that represents the on resistance of the switches. the value of this resistance is typically 100 . capacitor c2 represents the adc sampling capacitor and is typically 16 pf. c2 c1 r1 v dd d d 06448-010 figure 20. equivalent analog input circuit conversion phase: switch open track phase: switch closed for ac applications, removing high frequency components from the analog input signal is recommended by the use of a low-pass filter on the analog input pin. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input must be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc. this can necessitate the use of an input buffer amplifier. when no input amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k.
adis16204 rev. 0 | page 12 of 24 basic operation the adis16204 is designed for simple integration into industrial system designs, requiring only a power supply and a 4-wire, industry-standard spi. the spi provides access to the adis16204s register structure, which controls access to all sensor output data and controls for the devices programmable features. each register is 16 bits in length and has its own unique bit map. the 16 bits in each register consist of an upper byte (bit 8 to bit 15) and a lower byte (bit 0 to bit 7), each of which has its own 6-bit address. serial peripheral interface the adis16204 spi port includes four signals: chip select ( cs ), serial clock (sclk), data input (din), and data output (dout). the cs line enables the adis16204 spi port and frames each spi event. when this signal is high, the dout lines are in a high impedance state and the signals on din and sclk have no impact on operation. a complete data frame contains 16 clock cycles. because the spi port operates in full duplex mode, it supports simultaneous, 16-bit receive (din) and transmit (dout) functions during the same data frame. see table 2 , figure 2 , and figure 3 for detailed timing and operation of the spi port. writing to registers figure 21 displays a typical data frame for writing a command to a control register. in this case, the first bit of the din sequence is a 1, followed by a 0, the 6-bit address, and the 8-bit data com- mand. because each write command covers a single byte of data, two data frames are required when writing to the entire 16-bit space of a register. the din bits clock into the adis16204 on the rising edge of sclk. reading from registers reading the contents of a register requires a modification to the sequence in the din sequence figure 21 . as shown in figure 22 , the first two bits in the din sequence are 0, followed by six address bits. each register has two addresses (upper, lower), but either one can be used to access its entire 16 bits of data. the final 8 bits of the din sequence are irrelevant and can be counted as dont cares during a read command. during the next data frame, the dout sequence contains the registers 16-bit data. the adis16204 clocks out the first dout bit on the falling edge of the cs line and clocks out the rest of the dout bits on the falling edges of the sclk signal. although a single read command requires two separate data frames, the full duplex mode mini- mizes this overhead, requiring only one extra data frame when continuously sampling. cs sclk din w/r a5 a4 a3 a2 a1 a0 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 data frame write = 1 read = 0 register address data for write commands don?t care for read commands 06448-011 figure 21. din bit sequence address don?t care next command based on previous command data frame 16-bit register contents cs sclk din dout w/r bit zero data frame 06448-012 figure 22. spi sequence for read commands
adis16204 rev. 0 | page 13 of 24 data output register access table 6 provides an overview of each data output register, along with their function, address, and relevant decoding information. sensor output data the adis16204 provides access to x- and y-axis acceleration measurements, combined accelerations measurements (root sum square of x and y), peak acceleration, power supply meas- urements, temperature measurements, an auxiliary 12-bit adc channel, and the event-capture buffer memory. peak sample and hold output registers the adis16204 monitors the x, y and xy acceleration measurements and holds the maximum value and polarity for each parameter. the x_peak_out, y_peak_out, and xy_peak_out registers provide access to these maximum values. see the command register for clearing these registers. register access this output data is continuously updating internally, regardless of user read rates. the bit map in table 5 describes the structure of all output data registers in the adis16204. the upper byte is always first in register read sequences. table 5. output bit assignments msb lsb nd ea d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 the msb holds the new data (nd) indicator. when the output registers are updated with new data, the nd bit goes to a 1 state. after the output data is read, it returns to a 0 state. the ea bit is used to indicate a system error or an alarm condition that can result from a number of conditions, such as a power supply that is out of the specified operating range (see the status and diagnostics section for more details). the output data is either 12 bits or 14 bits in length. for all of the 12-bit output data, bit d13 and bit d12 are assigned dont care status. the output data register map is located in table 6 and provides all of the necessary details for accessing each registers data. figure 23 provides an example of the spi sequence. table 6. data output register information name function register resolution (bits) data format scale factor (per lsb) supply_out power supply 0x03, 0x02 12 binary 1.22 mv xaccl_out x-axis acceleration 0x05, 0x04 14 twos complement 17.125 m g yaccl_out y-axis acceleration 0x07, 0x06 14 twos complement 8.407 m g aux_adc auxiliary analog input data 0x09, 0x08 12 binary 0.61 mv temp_out 1 sensor temperature data 0x0b, 0x0a 12 binary ?0.47c x_peak_out 2 peak, x-axis acceleration 0x0d, 0x0c 14 twos complement 17.125 m g y_peak_out 2 peak, y-axis acceleration 0x0f, 0x0e 14 twos complement 8.407 m g xy_rss_out 3 x-y combined acceleration (rss) 0x19, 0x18 14 binary 17.125 m g xy_peak_out 2 ,3 peak, x-y combined output (rss) 0x1b, 0x1a 14 binary 17.125 m g capt_buf_1 4 capture buffer 1 output register 0x1d, 0x1c capt_buf_2 4 capture buffer 2 output register 0x1f, 0x1e see the alarm detection and event capture section, table 37 , and table 38 1 25c, nominal output is equal to 1278 lsb. 2 the peak levels in these registers accumulate, storing the greatest value measured (polarity is capturedexcept for xy_peak_ou t), until they are cleared using the command register. 3 this is a measure of the total shock absorbed by the package in the xy plane, and is the result of a root sum square of x and y acceleration measurements. 4 see the alarm detection and event capture section for more details. cs sclk din dout addr ess = 0 00101 w/r bit = 0 data = 1011 1101 1101 1110 new data, no alarm, xaccl_out = ?10.377 g 06448-013 figure 23. example of an output timing/coding diagram
adis16204 rev. 0 | page 14 of 24 programming and control control register overview the adis16204 offers many programmable features controlled by writing commands to the appropriate control registers. the following features are available for configuration: ? global commands ? calibration ? operational control ? sample rate ? power management ? dac output ? digital i/o ? operational status and diagnostics ? self-test ? status conditions ? alarms ? event capture control register structure the adis16204 uses a temporary, sram-based memory struc- ture to facilitate the control registers displayed in table 7 . the start-up configuration is stored in a flash memory structure that automatically loads into the control registers during the start-up sequence. each nonvolatile register has a corresponding flash memory location for storing the latest configuration contents. because flash memory has endurance limitations, the contents of each nonvolatile register must be stored to flash manually. note that the contents of the control register are only nonvola- tile when they are stored to flash. the flash update command, made available in the command register, provides this function. the endurance register provides a counter, which allows for memory reliability management against the flash memorys write cycle specification. table 7. control register mapping name type volatility 1 address bytes function reference table endurance r nonvolatile 0x01, 0x 00 2 flash memory write counter table 26 0x02 to 0x0f 14 output data registers table 6 xaccl_null r/w nonvolatile 0x11, 0x10 2 x-ax is offset null calibration register table 10 yaccl_null r/w nonvolatile 0x13, 0x12 2 y- axis offset null calibration register table 11 xaccl_scale r/w nonvolatile 0x15, 0x14 2 x- axis scale factor calibration register table 12 yaccl_scale r/w nonvolatile 0x17, 0x16 2 y- axis scale factor calibration register table 13 0x18 to to 0x1b 4 output data registers table 6 cap_buf_1 r volatile 0x1d, 0x1c 2 capture buffer output register 1 table 37 , table 38 cap_buf_2 r volatile 0x1f, 0x1e 2 capture buffer output register 2 table 37 , table 38 alm_mag1 r/w nonvolatile 0x21, 0x 20 2 alarm 1 amplitude threshold table 32 , table 34 alm_mag2 r/w nonvolatile 0x23, 0x 22 2 alarm 2 amplitude threshold table 33 , table 34 0x24 to 0x27 2 reserved alm_ctrl r/w nonvolatile 0x29, 0x28 2 alarm source control register table 30 , table 31 capt_pntr r/w volatile 0x2b, 0x2a 2 capture register address pointer table 39 , table 40 0x2a to 0x2f 6 reserved aux_dac r/w volatile 0x31, 0x30 2 auxiliary dac data table 19 , table 20 gpio_ctrl r/w volatile 0x33, 0x32 2 auxiliary digital i/o control register table 21 , table 22 msc_ctrl r/w nonvolatile 2 0x35, 0x34 2 miscellaneous control register table 24 , table 25 smpl_prd r/w nonvolatile 0x37, 0x36 2 ad c sample period control register table 15 , table 16 capt_cfg r/w nonvolatile 0x39, 0x38 2 capture configuration register table 35 , table 36 slp_cnt w volatile 0x3b, 0x3a 2 counter used to determine length of power-down mode table 17 , table 18 status r volatile 0x3d, 0x3c 2 system status register table 27 , table 28 command w n/a 0x3f, 0x3e 2 system command register table 8 , table 9 1 in order to establish nonvolatile status, the flash memory must be updated after updating the control registers. 2 bit 8 clears after the internal self-test sequence completes, effectively making this bit volatile.
adis16204 rev. 0 | page 15 of 24 global commands the adis16204 provides global commands, which simplify many common operations. the command register provides command bits for each function. writing a 1 to the assigned command bit exercises its function. the flash update copies the contents of all nonvolatile registers into their assigned, nonvolatile, flash memory locations. this process takes approximately 50 ms and requires a power supply that is within the specified operating range. after waiting the appropriate time for the flash update to complete, verify successful completion by reading the status register (flash update error = zero, if successful). if the flash update was not successful, reading this error bit will accomplish two things: (1) alert system processor to try again, and (2) clear the error flag, which is required for flash memory access. the software reset command restarts the internal processor, which loads all registers with the contents in their flash memory locations. the dac data latch command loads the contents of aux_dac into the dac latches. because the aux_dac contents must be updated one byte at a time, this command ensures a stable dac output voltage during updates. calibration commands the autonull command provides a simple method for removing offset from the sensor outputs. this command takes separate 64-sample measurements for each axis (x, y), then loads the opposite value into each axis offset null register. the accuracy of this operation depends on zero force or motion during the 64-sample timeframe. the factory calibration restore sets the scale and offset null registers (xaccl_null, for example) back to their default values. for more information on adis16204 calibration, see the calibration section. event capture commands the command register provides four different functions that simplify the process of using the event capture function. the reset-capture pointer function sets the contents of the capture pointer to its initial value of 0x0001. the clear capture flash, clear capture buffer, and capture flash copy commands are self- descriptive. the capture flash copy takes approximately 120 ms to complete and serves the purpose of copying the capture buffer into nonvolatile flash memory. see the alarm detection and event capture section for more information. table 8. command register definition address default format access 0x3f, 0x3e n/a n/a w only table 9. command bit descriptions bit description 15:11 not used 10 reset capture pointer (set capt_pntr to 0x0001) 9 clear capture flash (nonvolatile back-up) 8 clear capture buffer (sram) 7 software reset 6 copy capture buffer to nonvolatile flash 5 clear peak output register s, (reset them to 0x0000) 4 clear status register (reset all bits to 0) 3 flash updatesaves nonvolatile register settings 2 dac data latch 1 factory calibration restore 0 autonull calibration in addition to the factory calibration, the adis16204 provides a user configurable calibration for systems that require accuracy improvements. for example, a vehicle system may require better resolution to separate a minor bump from a hard brake event. in cases like this, the adis16204 provides configuration registers that adjust both offset and sensitivity (gain) on both x- and y-axes. the following relationship describes the calibration function: y = mx + b where: y is the calibrated output data. m is the scale factor multiplier [xaccl_scale/yaccl_scale]. x is the precalibration data. b is the offset adder [xaccl_null/yaccl_null]. assuming zero offset and nominal scale factor (sensitivity), the offset adjustment range for the x-axis is 35.054 g and 17.527 g for the y-axis. assuming zero offset, the scale factor adjustment range is 0 to 2. table 10. xaccl_null register definition address scale 1 default format access 0x11, 0x10 17.125 m g 0x0000 twos complement r/w 1 scale is the weight of each lsb. table 11. yaccl_null register definition address scale 1 default format access 0x13, 0x12 8.407 m g 0x0000 twos complement r/w 1 scale is the weight of each lsb. table 12. xaccl_scale register definition address scale 1 default 2 format access 0x15, 0x14 0.0488% 0x0800 binary r/w 1 scale is the weight of each lsb. 2 equates to a scale factor of one.
adis16204 rev. 0 | page 16 of 24 table 13. yaccl_scale register definition address scale 1 default 2 format access 0x17, 0x16 0.0488% 0x0800 binary r/w 1 scale is the weight of each lsb. 2 equates to a scale factor of one. table 14. calibration register bit descriptions bit description 15:12 not used 11:0 data bits operational control internal sample rate the internal sample rate defines how often data output variables are updated, independent of the rate at which they are read out on the spi port. the smpl_prd register controls the adis16204 internal sample rate and has two parts: a selectable time base and a multiplier. the following relationship produces the sample rate: t s = t b ( n b s + 1) where: t s is the sample period. t b is the time base. n b s is the increment setting. the default value is the maximum 4096 sps, and the contents of this register are nonvolatile. table 15. smpl_prd register definition address default format access 0x37, 0x36 0x0001 n/a r/w table 16. smpl_prd bit descriptions bit description 15:8 not used 7 time base 0 = 122.07 s, 1 = 3.784 ms 6:0 multiplier here is an example calculation of the sample period for the adis16204: if smpl_prd = 0x0007, b7 ? b0 = 00000111 b7 = 0 t b = 122.07 s b b6 b0 = 000000111 n s = 7 t s = t b (n b s + 1) = 122.07 s (7 + 1) = 976.56 s f s = 1M t s = 1024 sps the sample rate setting has a direct impact on the spi data rate capability. for sample rates of 1024 sps and above, the spi sclk can run at a rate up to 2.5 mhz. for sample rates below 1024 sps, the spi sclk can run at a rate up to 1 mhz. the sample rate setting also affects the power dissipation. when the sample rate is set below 1024 sps, the power dissipation typically reduces by a factor of 68%. the two different modes of operation offer a system-level trade-off between performance (sample rate, serial transfer rate) and power dissipation. power management in addition to offering two different performance modes for power optimization, the adis16204 offers a programmable shutdown period. writing the appropriate sleep time to the slp_cnt register shuts the device down for the specified time. the following example provides an illustration of this relationship: b7 b0 = 00000110 sleep period = 3 seconds after completing the sleep period, the adis16204 returns to normal operation. table 17. slp_cnt register definition address scale 1 default format access 0x3b, 0x3a 0.5 sec 0x0000 binary w only 1 scale is the weight of each lsb. table 18. slp_cnt bit descriptions bit description 15:8 not used 7:0 data bits auxiliary dac the auxiliary dac provides a 12-bit level adjustment function. the aux_dac register controls the operation of this feature. it offers a rail-to-rail buffered output that has a range of 0 v to 2.5 v. the dac can drive its output to within 5 mv of the ground reference when it is not sinking current. as the output approaches ground, the linearity begins to degrade (100 lsb beginning point). as the sink current increases, the nonlinear range increases. the dac output latch function, contained in the command register, provides continuous operation while writing to each byte of this register. the contents of this register are volatile, which means that the desired output level must be set after every reset and power cycle event. table 19. aux_dac register definition address scale 1 default format access 0x31, 0x30 0.6105 mv 0x0000 binary r/w 1 scale is the weight of each lsb. in this case, it repres ents 4095 codes over the 2.5 v range out of output voltage. table 20. aux_dac bit descriptions bit description 15:12 not used 11:0 data bits
adis16204 rev. 0 | page 17 of 24 general-purpose i/o the adis16204 provides two general-purpose pins that enable digital i/o control using the spi. the gpio_ctrl control register establishes the configuration of these pins and handles the spi-to-pin controls. each pin provides the flexibility of both input (read) and output (write) operations. for example, writing a 0x0202 to this register establishes line 1 as an input and line 2 as an output that is in a 1 state. writing 0x0000 to this register establishes both lines as inputs. when one (or both) of these lines is configured as an input, reading the assigned bit (bit 8 and/or bit 9) provides access to the input on this input pin. the digital i/o lines are also available for data-ready and alarm/ error indications. in the event of conflict, the following priority structure governs the digital i/o configuration: 1. gpio_ctrl 2. msc_ctrl 3. alm_ctrl table 21. gpio_ctrl register definition address default format access 0x33, 0x32 0x0000 n/a r/w table 22. gpio_ctrl bit descriptions bit description 15:10 not used 9 general-purpose i/o line 2 polarity 1 = high, 0 = low 8 general-purpose i/o line 1 polarity 1 = high, 0 = low 7:2 not used 1 general-purpose i/o line 2, data direction control 1 = output, 0 = input 0 general-purpose i/o line 1, data direction control 1 = output, 0 = input status and diagnostics the adis16204 provides a number of status and diagnostic functions. table 23 provides a summary of these functions, along with their appropriate control registers. table 23. status and diagnostic functions function register data-ready i/o indicator msc_ctrl self-test, mechanical check for mems sensor msc_ctrl software check for error conditions status flash memory endurance endurance data-ready i/o indicator the data-ready function provides an indication of new output data. the msc_ctrl register provides the opportunity to configure either of the general-purpose i/o pins (dio1 and dio2) as a data-ready indicator signal. when configured as a data ready indicator, the duty cycle is 20% (10% tolerance). self-test the msc_ctrl register also provides a self-test function that verifies the mechanical integrity of the mems sensor. self- test exercises the mechanical structure and signal conditioning circuit: from sensor element to data out. the internal test provides a simple, two-step process for checking the mems sensor: (1) start the proce ss by writing a 1 to bit 8 in the msc_ctrl register, (2) wait 35 ms, and (3) check the result by reading bit 5 of the status register. the device is configured to perform a self-test at power on. writing a 1 to bit 10 of the msc_ctrl register disables this function for future start-up sequences, reducing the start-up time. for reference, the result of the electrostatic deflection of each axis is available by reading the xaccl_out and/or yaccl_out registers. as an additional indicator of self-test, the new data bit is not active while in this mode. table 24. msc_ctrl register definition address default format access 0x35, 0x34 0x0000 n/a r/w table 25. msc_ctrl bit descriptions bit description 15:12 not used 11 store capture to flash after capture buffer fills up 1 = enabled, 0 = disabled 10 self-test at power-on: 1 = disabled, 0 = enabled 9 not used 8 self-test enable (temporary, bit is volatile) 1 = enabled, 0 = disabled 7:3 not used 2 data-ready enable 1 = enabled, 0 = disabled 1 data-ready polarity 1 = active high, 0 = active low 0 data-ready line select: 1 = dio2, 0 = dio1 flash memory endurance the endurance register maintains a running count of writes to the flash memory. this provides a convenient tool for managing the reliability of the on-chip memory. once it reaches its maxi- mum value of 32,767, it wraps around to zero and starts over. table 26. endurance register definition address default format access 0x01, 0x00 n/a binary r only
adis16204 rev. 0 | page 18 of 24 status conditions the status register contains the following error-condition flags: alarm conditions, self-test status, spi communication failure, capture buffer full, control register update failure, and power supply out of range. see table 27 and table 28 for the appropriate register access and bit assignment for each flag. the bits assigned for checking power supply range automati- cally reset to zero when the error condition no longer exists. clearing the remaining error-flag bits requires a single write command to the command register (write a 1 to bit 4). see table 8 and table 9 for the configuration details of the command register. if the error condition still exists after exercising the command register to clear the bits, the appro- priate error flag bit returns to 1 during the next sampling cycle. all bits in the status register are volatile. table 27. status register definition address default format access 0x3d, 0x3c 0x0000 n/a r only table 28. status bit descriptions bit description 15:13 not used 12 capture buffers full 11:10 not used 9 alarm 2 status 1 = active, 0 = inactive 8 alarm 1 status 1 = active, 0 = inactive 7:6 not used 5 self-test diagnostic error flag 1 = error condition, 0 = normal operation 4 not used 3 spi communications failure 1 = error condition, 0 = normal operation 2 flash update failed 1 = error condition, 0 = normal operation 1 power supply above 3.625 v 1 = above 3.625 v, 0 = below 2.975 v (normal) 0 power supply below 2.975 v 1 = below 2.975 v, 0 = above 2.975 v (normal) alarm detection and event capture the adis16204 provides alarm detection and event capture functions, which monitor critical internal and external operating conditions. six factory standard alarms monitor the aids16204 for normal operation. two programmable alarms provide monitoring for system-critical conditions, which reduces external processing burden for this function. alarm monitoring includes both software (status register) and hardware options (dio1 and dio2 configuration, alm_ctrl register). in addition, the programmable alarms can trigger an event capture function, which provides time recording, much like a single event capture function on a digital oscilloscope. table 29 provides a summary of the functions available for configuring the alarms. alarm configuration mark, i am just realizing this now, but i cannot bold normal text just for 1. program the output data to monitor. essentially, this establishes the trigger source, by configuring the upper byte of the alm_ctrl register. see table 31 for the proper bit assignments. for example, the following pseudo code establishes x acceleration as the trigger for alarm 2 and y accel- eration as the trigger for alarm 1: ? write 0x23 to address 0x29 [alm_ctrl]. 2. program the trigger levels and polarity. this requires two write commands for each alarm, to the alm_mag1 and alm_mag2 registers. for example, use the following pseudo code to establish greater than 7.4 g as the trigger threshold for both channels: ? write 0x81 to address 0x21 [alm_mag1]. ? write 0xb0 to address 0x20 [alm_mag1]. ? write 0x83 to address 0x23 [alm_mag2]. ? write 0x70 to address 0x22 [alm_mag2]. the alm_mag1 and alm_mag2 values are calculated by: x = 7.4 g = 432 codes = 00 0001 1011 0000 (bit 0 to bit 13) y = 7.4 g = 880 codes = 00 0011 0111 0000 (bit 0 to bit 13) bit 15 in both registers must be set to 1 in order to denote greater than polarity. 3. set up a digital i/o line as an alarm indicator. this step requires configuration of the lower byte in the alm_ctrl. if software monitoring, using the status register, is the preferred alarm-checking method, then this step is not required. the following pseudo code establishes digital i/o line 2 as a positive signal, alarm indicator: ? write 0x07 to address 0x28 [alm_ctrl]. see table 31 for the configuration options available for this function. as noted earlier, the digital i/o lines are shared, so use of them as an alarm indicator requires that it not be in use as a data-ready or general-purpose i/o pin.
adis16204 rev. 0 | page 19 of 24 table 29. alarm and event capture configuration registers register parameter/function default setting alm_ctrl alarm trigger source none alm_ctrl capture buffer triggers disabled alm_ctrl digital alarm output disabled alm_mag1/ alm_mag 2 alarm trigger levels 0 alm_mag1/ alm_mag 2 alarm trigger directions less than capt_cfg capture data sources 1: x acceleration 2: y acceleration capt_cfg capture buffer size 1024 samples capt_cfg pretrigger data size 128 samples command reset capture pointer n/a command clear capture buffer n/a command clear capture flash n/a command clear buffer full flag n/a command save captured data to nonvolatile flash n/a msc_ctrl autosave captured data to nonvolatile flash disabled smpl_prd sample rate 4096 sps table 30. alm_ctrl register definition address default format access 0x29, 0x28 0x0000 n/a r/w table 31. alm_ctrl bit descriptions bit value description 15:12 trigger source selection, alarm 2 0000 disable 0001 power supply 0010 x-acceleration 0011 y-acceleration 0100 auxiliary adc 0101 temperature sensor 1000 xy rss acceleration 11:8 trigger source selection, alarm 1 (see alarm2) 7 not used 6 capture trigger activation, alarm 2 1 = enabled, 0 = disabled 5 not used 4 capture trigger activation, alarm 1 1 = enabled, 0 = disabled 3 not used 2 alarm indicator, using dio1/2 1 = enabled, 0 = disabled 1 alarm indicator polarity 1 = active high, 0 = active low 0 alarm indicator line selection 1 = dio2, 0 = dio1 table 32. alm_mag1 register definition address default format access 0x21, 0x20 0x0000 n/a r/w table 33. alm_mag2 register definition address default format access 0x23, 0x22 0x0000 n/a r/w table 34. alm_mag1/alm_mag 2 bit designations bit description 15 comparison polarity 1 = greater than, 0 = less than 14 not used 13:0 data bits: format matches source data format (see table 5 and table 6 ) event capture overview the adis16204 also provides a dual-channel, capture function. figure 24 provides an example of a captured waveform. a dedi- cated set of programmable control registers govern the operation of this function, controlling the data source: trigger settings (level, direction and data source), memory depth, pretrigger data length, and data storage. in systems that require specific event monitoring, this feature simplifies system integration by reducing the burden on the systems processor. one convenient feature is the fact that the trigger source does not have to be the data that is captured. 5 10 15 20 0 ?5 ?15 ?10 ?20 0 100 200 300 400 500 600 700 800 900 1000 y-axis impact magnitude ( g ) sample ? f s = 4096sps trigger threshold: 7.4 g data source: y-axis acceleration 06448-014 pre-trigger data length figure 24. event capture example event capture configuration the event capture buffers use the alarms as their trigger source. therefore, the first two configuration steps are the same. after setting the trigger data source(s) and threshold(s), follow these steps to complete the event capture setup: 1. program the data source to capture. this requires a single write cycle, to configure the upper byte of the capt_cfg register. for example, use the following pseudo code to set x acceleration and y acceleration as the data sources for capture buffer 2 and capture buffer 1 respectively: ? write 0x23 to address 0x39 [capt_cfg].
adis16204 rev. 0 | page 20 of 24 2. configure the capture back-up memory. setting bit 11 of the msc_ctrl register to a 1 enables the event capture back-up function, effectively making it nonvolatile. when enabled, this function copies the contents of the capture buffer (right after it fills) to flash memory and restores it upon reset or powering the device on. it continues to do so until the buffer is cleared, using the command register. to enable this feature, use the following pseudo code: ? write 0x08 to address 0x35 [msc_ctrl]. 3. clear the capture memory locations. use the following pseudo code to clear both the normal capture locations (sram) and their respective flash memory locations: ? write 0x03 to address 0x3f [command]. 4. set up a digital i/o line as an alarm indicator. 5. set each alarm as a trigger source for the buffer. these steps require configuration of the lower byte in the alm_ctrl register. the following pseudo code establishes digital i/o line 2 as a positive signal, alarm indicator, if necessary. it also arms both triggers for the event recorder. ? write 0x57 to address 0x28 [alm_ctrl]. if a digital alarm indicator function were not required, the pseudo code would be: ? write 0x50 to address 0x28 [alm_ctrl]. table 35. capt_cfg register definition address scale default format access 0x39, 0x38 n/a 0x327a n/a r/w table 36. capt_cfg bit descriptions bit description 15:12 data source for capture buffer 2 0001= power supply 0010= x-axis acceleration 0011= y-axis acceleration 0100= auxiliary adc 0101= temperature sensor 1000= xy rss acceleration 11:8 data source for capture buffer 1 (see capture buffer 2 for binary coding) 7:4 pretrigger length: power of two setting determines length. 0111b = 7d, which corresponds to 2 7 = 128 samples. if this setting is greater than the data length, its value is truncated and all captured samples are prior to the trigger 3:0 capture buffer length: power of two setting determine length. 1010b = 10d, which corresponds to 2 10 = 1024 samples. the lowest setting is a 3, which corresponds to 8 samples event capture data access two output registers provide the necessary access for the adis16204s capture buffers: capt_buf_1 and capt_buf_2. at the completion of a capture event, the contents of theses registers contain the first sample from each buffer. figure 25 provides a diagram that displays the role played by the capt_pntr register in this process. this register provides a pointer function and automatically increments every time one of the cap_buf_x registers are read. if efficient data transfer rates are a primary goal, then read all of the contents of one buffer, before moving to the other buffer. because the capt_pntr offers both read and write access, individual buffer locations can be accessed by writing the sample number into this register. 06448-030 capt_pntr buffer 1 buffer 2 capt_buf_1 capt_buf_2 user accesible internal memory strucutre figure 25. event capture buffer memory structure table 37. capture register definitions address address format access capt_buf_1 0x1d, 0x1c capt_buf_2 0x1e, 0x1f the format and scale match that of the output data being monitored r only table 38. capt_buf_1 and ca pt_buf_2 bit descriptions bit description 15 not used 14 error/alarm condition (use to identify transition between pre-trigger and post-trigger data) 13:0 data bits. format matches that of the data source table 39. capt_pntr register definition address scale default format access 0x2b, 0x2a n/a n/a binary r/w table 40. capt_pntr bit descriptions bit description 15:11 not used 10:0 capture address pointer: a binary number from 1 to 1024, which identifies the address of each individual capture buffer sample.
adis16204 rev. 0 | page 21 of 24 second-level assembly the adis16204 can be attached to the second-level assembly board using sn63 (or equivalent) or a pb-free solder. figure 26 and table 41 provide acceptable solder reflow profiles for each solder type. note that these profiles may not be the optimum profile for the users application. in no case should 260c be exceeded. it is recommended that the user develop a reflow profile based upon the specific application. in general, keep in mind that the lowest peak temperature and shortest dwell time above the melt temperature of the solder results in less shock and stress to the product. in addition, evaluating the cooling rate and peak temperature can result in a more reliable assembly. 06448-031 t p t l t25c to peak t s preheat critical zone t l to t p temperature time ramp-down ramp-up t smin t smax t p t l figure 26. acceptable solder reflow profiles table 41. acceptable solder reflow profiles 1 condition profile feature sn63/pb37 pb-free average ramp rate (t l to t p ) 3c/sec max 3c/sec max preheat minimum temperature (t smin ) 100c 150c maximum temperature (t smax ) 150c 200c time (t smin to t smax ) (t s ) 60 sec to 120 sec 60 sec to180 sec t smax to t l ramp-up rate 3c/sec 3c/sec time maintained above liquidous temperature(t l ) liquidous temperature (t l ) 183c 217c time (t l ) 60 sec to 150 sec 60 sec to 150 sec peak temperature (t p ) 240c + 0c/C5c 260c + 0c/C5c time within 5c of actual t p 10 sec to 30 sec 20 sec to 40 sec ramp-down rate 6c/sec max 6c/sec max time 25c to t p 6 min max 8 min max 1 per ipc/jedec j-std-020c.
adis16204 rev. 0 | page 22 of 24 outline dimensions 022007-b side view top view bottom view pin 1 indicator 1.000 bsc (16 ) 3.90 max 9.20 typ 1 4 5 8 9 12 13 16 9.35 max 5.391 bsc (4 ) 2.6955 bsc (8 ) 5.00 typ 8.373 bsc (2 ) 0.200 min (all sides ) 0.797 bsc (12 ) 0.373 bsc (16 ) figure 27. 20-terminal land grid array [lga] (cc-16-2) dimensions shown in millimeters ordering guide model temperature range package description package option adis16204bccz 1 ?40c to +105c 16-terminal la nd grid array [lga] cc-16-2 adis16204/pcbz 1 evaluation board 1 z = rohs compliant part.
adis16204 rev. 0 | page 23 of 24 notes
adis16204 rev. 0 | page 24 of 24 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06448-0-6/07(0)

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